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this document is a general product description and is subject to change without notice. hynix semiconductor inc does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.0 2 / apr. 2002 hynix semiconductor hy62uf16800 b series 512 kx16bit full cmos sram document title 512k x16 bit 3.0v super low power full cmos slow sram revision history revision no history draft date remark 00 initial release may.29.2001 preliminary 01 dc para change mar.20.2002 icc 4ma 3ma icc1(min) 40ma 20ma icc1(1us) 8ma 2ma isb 0.1ma 0.3ma isb1 25ua 15ua iccdr 12ua 6ua 02 pin connection apr.10.2002 e3 dnu e3 nc
HY62UF16800B rev.0 2 / apr. 2002 2 description the h y62uf16800b is a high speed, super low power and 8 mbit full cmos sram organized as 5 2 4 , 288 words by 16bits. the HY62UF16800B uses high performance full cmos process technology and is designed for high speed and low power circuit technology. it is particula rly well - suited for the high density low power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1. 2 v. features fully static operation and tri - state output ttl compatib le inputs and outputs battery backup(ll/sl - part) - 1. 2 v(min) data retention standard pin configuration - 48 - fbga product voltage speed operation standby current(ua) temperatu re no. (v) (ns) current /icc (ma) ll ( c ) HY62UF16800B - c 2.7~3.3 55/70/85 3 15 0~70 HY62UF16800B - i 2.7~3.3 55/70/85 3 15 - 40~85 note 1. c : commercial , i : industrial 2. current value is max. pin connection ( top view ) block diagram pin description pi n name pin fun c tion pin name pin fun c tion /cs 1, cs2 chip select i/o1~i/o16 data input s / output s /we write enable a0~a1 8 address input s /oe output enable vcc power( 2.7v~3.3v ) /lb low er byte control(i/o1~i/o8) vss ground /ub upper byte control(i/o9~i/o 16) nc no connection m emory array 512k x 16 row decoder sense amp write driver data i/o buffer i/o1 i/o8 i/o9 i/o16 column decoder block decoder pre de coder add input buffer a18 /cs1 /oe /lb /ub /we cs2 1 2 3 4 5 6 a b c d e f g h /lb io 9 io1 0 /oe a0 a1 a2 cs2 /ub a3 a 4 /cs 1 io1 io1 1 a 5 a 6 io2 io3 vss io1 2 a 17 a 7 io4 vcc vcc io1 3 nc a16 io5 vss io1 5 io1 4 a 14 a1 5 io 6 io 7 io16 nc a1 2 a1 3 /we io8 a18 a 8 a9 a1 0 a1 1 nc
HY62UF16800B rev.0 2 / apr. 2002 2 ordering information part no. speed power package temp. hy62uf16800 b - d f c 55/70/85 ll - part fbga c HY62UF16800B - d fi 55/70/85 ll - part fbga i note 1. c : commercial , i : industrial absolute maximum ratings (1) symbol paramete r rating unit remark v in, v out input/output voltage - 0.3 to vcc +0.3 v vcc power supply - 0.3 to 4. 6 v 0 to 70 c HY62UF16800B - c t a operating temperature - 40 to 85 c HY62UF16800B - i t stg storage temperature - 55 to 150 c p d power dissipation 1.0 w t solder ball soldering temperature & time 260 10 c sec note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and the functional op eration of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. truth table i/o pin /cs1 cs2 /we /oe /lb /ub mode i/o1~i/o8 i/o9~i/o16 power h x x x x x hi - z hi - z x l x x x x hi - z hi - z x x x x h h des elected hi - z hi - z standby l h h h l x hi - z hi - z l h h h x l output disabled hi - z hi - z active l h d out hi - z h l hi - z d out l h h l l l read d out d out active l h d in hi - z h l hi - z d in l h l x l l write d in d in active note: 1. h=v ih , l=v il , x=don't care ( v ih or v il ) 2. ub, lb(upper, lower byte enable) these active low inputs all ow individual bytes to be written or read. when / lb is low, data is written or read to the lower byte, i/o1 - i/o8. when / ub is low, data is written or read to the upper byte, i/o9 - i/o16.
HY62UF16800B rev.0 2 / apr. 2002 3 recommended dc operating condition symbol parameter m in. typ. max. unit vcc supply voltage 2.7 3.0 3.3 v vss ground 0 0 0 v v ih input high voltage 2.2 - vcc+0. 3 v v il input low voltage - 0. 3 (1) - 0. 6 v note : 1. vil = - 1.5v for pulse width less than 30ns dc electrical characteristics vcc = 2.7v~3. 3v , t a = 0 c to 70 c/ - 40 c to 85 c sym parameter test condition min ty p 1. max unit i li input leakage current vss < v in < vcc - 1 - 1 ua i lo output leakage current vss < v out < vcc, /cs 1 = v ih or cs2=v il or / oe = v ih or /we = v il or / ub = v ih , /lb = v ih - 1 - 1 ua icc operating power supply curren t /cs 1 = v il , cs2=v ih , v in = v ih or v il, i i/o = 0ma 3 ma /cs 1 = v il, cs2 = v ih , v in = v ih or v il, cycle time = min, 100% duty, i i/o = 0ma 20 ma i cc1 average operating current /cs 1 < 0.2v , cs2 > vc c - 0.2v, v in < 0.2v or v in > vcc - 0.2v , cycle time = 1us, 100% duty, i i/o = 0ma 2 ma i sb standby current (ttl input) /cs 1 = v ih or cs2 = v il or /ub, /lb = v ih v in = v ih or v il 0.3 ma i sb1 standby current (cmos input) /cs 1 > vcc - 0.2v or cs2 < vss + 0.2v or /ub, /lb > vcc - 0.2v v in > vcc - 0.2v or v in < vss + 0.2v ll 1 15 ua v ol output low i ol = 2.1ma - - 0. 4 v v oh output high i oh = - 1.0ma 2. 4 - - v note : 1. typical values are at vcc = 3.0v , t a = 25 c 2. typical values are no t 100% tested capacitance (temp = 25 c , f = 1.0mhz) symbol parameter condition max. unit c in input capacitance (add, /cs 1,cs2,/lb,/ub , /we, /oe) v in = 0v 8 pf c out output capacitance (i/o) v i/o = 0v 10 pf note : these parameters are sampled and not 100% tested
HY62UF16800B rev.0 2 / apr. 2002 4 ac characteristics vcc = 2.7v~3.3v , t a = 0 c to 70 c/ - 40 c to 85 c unless otherwise specified - 55 - 70 - 85 # symbol parameter min. max. min. max. min max. read cycle 1 trc read cycle time 55 - 70 - 85 - ns 2 taa addre ss access time - 55 - 70 - 85 ns 3 tacs chip select access time - 55 - 70 - 85 ns 4 toe output enable to output valid - 30 - 35 - 40 ns 5 tba /lb, /ub access time - 55 - 70 - 85 ns 6 tclz chip select to output in low z 10 - 10 - 10 - ns 7 tolz output enable to output in low z 5 - 5 - 5 - ns 8 tblz /lb, /ub enable to output in low z 10 - 10 - 10 - ns 9 tchz chip deselection to output in high z 0 30 0 30 0 30 ns 10 tohz out disable to output in high z 0 30 0 30 0 30 ns 11 tbhz /lb, /ub disable to ou tput in high z 0 30 0 30 0 30 ns 12 toh output hold from address change 10 - 10 - 10 - ns write cycle 13 twc write cycle time 55 - 70 - 85 - ns 14 tcw chip selection to end of write 50 - 60 - 70 - ns 15 taw address valid to end of write 50 - 60 - 70 - ns 16 tbw /lb, /ub valid to end of write 50 - 60 - 70 - ns 17 tas address set - up time 0 - 0 - 0 - ns 18 twp write pulse width 45 - 50 - 60 - ns 19 twr write recovery time 0 - 0 - 0 - ns 20 twhz write to output in high z 0 20 0 20 0 25 ns 21 tdw data to write time overlap 25 - 30 - 35 - ns 22 tdh data hold from write time 0 - 0 - 0 - ns 23 tow output active from end of write 5 - 5 - 5 - ns ac test conditions t a = 0 c to 70 c / - 40 c to 85 c , unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rise and fall time 5ns input and output timing reference level 1.5v tclz,tolz,tblz,tchz,tohz,tbhz,twhz,tow cl = 5 pf + 1ttl load output load other cl = 30pf + 1ttl load ac test loads d out 1728 ohm cl(1) 1029 ohm v tm = 2.8v note 1 . including jig and scope capacitance unit
HY62UF16800B rev.0 2 / apr. 2002 5 timing diagram read cycle 1(note 1 ,4 ) read cycle 2(note 1,2,4) trc taa data valid previous data toh toh addr data out read cycle 3(note 1, 2 ,4) /cs1 /ub, /lb tacs data valid tclz(3) tchz(3) data out cs2 notes: 1. read cycle occurs whenever a high on the /we and /oe is low, while /ub and / or /lb and /cs 1 and cs2 are in active status. 2. /oe = v il 3. transition is measured + 200mv from steady state voltage. this parameter is sampled and not 100% tested. 4. /cs 1 in hi gh for the standby, low for active cs 2 in low for the standby, high for active . /ub and /lb in high for the standby, low for active data valid high - z addr data out trc / cs1 cs2 / ub ,/ lb / oe taa tacs tba toe tclz (3) tblz (3) t olz (3) toh t chz (3) t bhz (3) tohz (3)
HY62UF16800B rev.0 2 / apr. 2002 6 write cycle 1 (1,4,8) (/we controlled) write cycle 2 (note 1,4, 8) (/cs1, cs2 contr olled) data valid addr data out / cs1 cs2 / ub , / lb / we twc tcw twr (2) tbw taw twp data in high-z tas twhz (3,7) tdw tdh tow (5) ( 6 ) data valid addr data out / cs1 cs2 / ub, / lb / we twc tcw twr (2) tbw taw twp data in tdw tdh high - z high - z tas
HY62UF16800B rev.0 2 / apr. 2002 7 notes: 1. a write occurs during the overlap of a low /we , a low /cs 1, a high cs2 and a low /ub and/or /lb . 2. twr is measured from the earlier of /cs 1 , /lb, /ub, or /we going high or cs2 going low to the end of write c ycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the /cs 1 , /lb and /ub low transition and cs2 high transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5 . q(data out) is the same phase with the write data of this write cycle. 6. q(data out) is the read data of the next address. 7. transition is measured + 200mv from steady state. this parameter is sampled and not 100% tested. 8. /cs 1 in high for the standby, low for active cs 2 in low for the standby, high for active . /ub and /lb in high for the standby, low for active data retention electric characteristi c t a = 0 c to 70 c / - 40 c to 85 c symbol parameter test condition min typ 1. max unit v dr vcc for data retention /cs 1 > vcc - 0.2v or cs2 < vss + 0.2v or /ub, /lb > vcc - 0.2v, v in > vcc - 0.2v or v in < vss + 0.2v 1. 2 - 3.3 v iccdr data retention cu rrent vcc= 1.5v , /cs 1 > vcc - 0.2v or cs2 < vss + 0.2v or /ub, /lb > vcc - 0.2v v in > vcc - 0.2v or v in < vss + 0.2v ll - 1.0 6 ua t cdr chip deselect to data retention time 0 - - ns tr operating recovery time see data retention timing diagram trc - - ns notes: 1. typical values are under the condition of t a = 25 c . 2. trc is read cycle time.
HY62UF16800B rev.0 2 / apr. 2002 8 data retention timing diagram 1 / cs1 vdr cs1>vcc-0.2v tcdr tr vss vcc 2.7v vih data retention mode data retention timing diagram 2 0.4v vdr tcdr tr vss vcc cs2 2.7v data retention mode cs2<0.2v
HY62UF16800B rev.0 2 / apr. 2002 9 package information 48ball fine pitch ball grid array package (f) bottom view top view b a a1 corner index area 6 5 4 3 2 1 a a b c d c c1 e f g c1/2 h b1/2 b1 side view 5 e1 e2 c e seating plane 4 a r 3 d(diameter) symbol min. typ. max. a - 0.75 - b - 3.75 - b1 5.9 6.0 6.1 c - 5.25 - c1 8.4 8.5 8.6 d 0.3 0.35 0.4 e 0.9 1.0 1.10 e1 - 0.76 - e2 0.20 0.25 0.30 r - - 0. 08 note 1. dimensioning and tolerancing per asme y14. 5 m - 1994. 2. all dimensions are millimeters. 3. dimension ?d? is measured at the maximum solder ball diameter in a plane parallel to datum c. 4. primary datum c(seating plane) is defined by the crown of the solder balls. 5 . this is a controlling dimension.
HY62UF16800B rev.0 2 / apr. 2002 10 marking instruction package marking example h y u f 6 0 0 b c s s t y w w p x x x x x k o r fbga index hyuf680 0 b : part name c : power consumption - d : low low power ss : speed - 55 : 55 ns - 70 : 70 ns t : temperature - c : commercial ( 0 ~ 70 c ) - i : industrial ( - 40 ~ 85 ) y : year (ex : 0 = year 2000, 1= year 2001) ww : work week ( ex : 12 = work week 12 ) p : process code xxxxx : lot no. kor : origin country note - capital letter : fixed i tem - small letter : non - fixed item package marking example h y f 6 8 c s s t y w w p x x x x x k o r index : part name c : power consumption - d : low low power ss : speed - 55 : 55 ns - 70 : 70 ns t : temperature - c : commercial ( ) - i : industrial ( - ) y : year (ex : 0 = year 2000, 1= year 2001) ww : work week ( ex : 12 = work week 12 ) p : process code xxxxx : lot no. kor : origin country note - capital letter : fixed item - small letter : non - fixed item c - 85 : 85 ns - package marking example h y u f 6 0 b c s s t y w w p x x x x x k o r fbga index : part name c : power consumption - d : low low power ss : speed - 55 : 55 ns - 70 : 70 ns t : temperature - c : commercial ( 0 ~ 70 c ) - i : industrial ( - 40 ~ 85 ) y : year (ex : 0 = year 2000, 1= year 2001) ww : work week ( ex : 12 = work week 12 ) p : process code xxxxx : lot no. kor : origin country note - capital letter : fixed it em - small letter : non - fixed item package marking example h y f 6 8 c s s t y w w p x x x x x k o r index : part name c : power consumption - d : low low power ss : speed - 55 : 55 ns - 70 : 70 ns t : temperature - c : commercial ( ) - i : industrial ( - ) y : year (ex : 0 = year 2000, 1= year 2001) ww : work week ( ex : 12 = work week 12 ) p : process code xxxxx : lot no. kor : origin cou ntry note - capital letter : fixed item - small letter : non - fixed item c - 85 : 85 ns -

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